Solved Question Paper for Assistant Director (Systems) in Directorate of Income Tax Systems & Senior Scientific Assistants (Computer) in DGAQA, Ministry of Defence conducted by UPSC

31. Which one of the following registers facilitates referencing parameters passed on the stack in 8086 architecture?
(a) DI and SI index registers
(b) CS and DS segment registers
(c) SP and BP pointer registers
(d) AX and DX general purpose registers

Answer: (c)

32. Consider the following statements:
1. Clear instruction register
2. Clear accumulator
3. Initialize program counter
4. Reset the processor
5. Clear all flags

Which of the above statements is/are essential in a program which uses subroutines?
(a) 1 only
(b) 1 and 4 only
(c) 5 only
(d) 1, 2, 3, 4 and 5

Answer: (a)

33. The contents of DE and HL register pairs after the execution of the following
instructions are:
(a) 0200𝐻 ,2700𝐻
(b) 2700𝐻 ,0200𝐻
(c) 2500𝐻 ,0200𝐻
(d) 0200𝐻 ,2500𝐻

Answer: (b)

34. How many times does the loop execute before coming out of the loop from the following instructions?
(a) 0
(b) 255
(c) 256
(d) 555

Answer: (c)

35. The instruction format for a processor has 1 bit for indirection, 6 bits for opcode and 9 bits for address of an operand. What is the maximum number of possible instructions, theoretically?

Answer: (c)

36. For a 32 bit processor with a 32 bit instruction format in which the first 10 bits contain the opcode and the remaining bits contain an operand address. What is the maximum directly addressable memory space?
(a) 16 MB
(b) 4 GB
(c) 1 KB
(d) 4 MB

Answer: (a)

37. Consider the following statements:
1. Vertical micro-programmed control unit operates faster than horizontal micro-programmed control unit
2. Direct microprogramming results in very short micro-instructions
3. Hardwired control unit operates fastest
4. Micro-programming enables backward compatibility of programs

Which of the above statements are correct?
(a) 3 and 4
(b) 1 and 2
(c) 2 and 3
(d) 1 and 4

Answer: (a)

38. If an instruction requires ′𝑖′ microseconds for execution and page fault requires ‘𝑗’ microseconds for resolving, and average page fault occurs every ‘𝑘’ instruction, then effective instruction time will be
(a) (𝑖+𝑗)∗𝑘
(b) (𝑖+𝑗)/𝑘
(c) 𝑖+(𝑗/𝑘)
(d) 𝑖+𝑗∗𝑘

Answer: (c)

39. The cache memory of 1 𝑘 words uses direct mapping with a block size of 4 words. How many blocks can the cache accommodate?
(a) 128 words
(b) 256 words
(c) 512 words
(d) 1024 words

Answer: (b)

40. How many NAND Gates are required to implement the Boolean function?
F = BC′+A(B +CD)
(a) 3
(b) 4
(c) 5
(d) 6

Answer: (c)

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