81. For vectors, 

The magnitude of 5𝐴−2𝐵 will be:

(a) √969

(b) √699

(c) √696

(d) √669

Answer: (a)

82. A zero operand computer always keeps operands in:

1. Stack

2. General Purpose Register (GPR)

3. Program counter

(a) 1 only

(b) 2 only

(c) 3 only

(d) 1, 2 and 3

Answer: (a)

83. In a 8051 microprocessor, PCON register controls the baud rate in:

1. Synchronous transmission

2. Asynchronous transmission

(a) 1 only

(b) 2 only

(c) Both 1 and 2

(d) Neither 1 nor 2

Answer: (b)

84. Which of the following specifications are to be mentioned in VLSI design?

1. The algorithm to be implemented with mathematical representation

2. Number of inputs and outputs in the design and number of bits used in internal arithmetic operation

3. Number of clock signals and maximum clock frequency

4. Area and power dissipation in the chip

(a) 1, 2 and 3 only

(b) 1, 2 and 4 only

(c) 1, 3 and 4 only

(d) 1, 2, 3 and 4

Answer: (d)

85. Which of the following properties are correct for Region of Convergence (ROC)?

1. It is a ring or disk in the 𝑧 -plane centered at the origin

2. It cannot contain any poles

3. It is of a LTI stable system contains the unit circle

4. It must be a connected region

(a) 1, 2 and 3 only

(b) 1, 2 and 4 only

(c) 1, 3 and 4 only

(d) 1, 2, 3 and 4

Answer: (d)

86. The total number of complex additions for evaluating a DFT using DIT-FFT  is:

Answer: (b)


(a) 20 kHz

(b) 24 kHz

(c) 28 kHz

(d) 32 kHz

Answer: (d)

88. A reserved area in RAM used for temporary storage of data, return addresses and content of registers during subroutine calls and interrupts is called:

(a) Accumulator

(b) Flags

(c) Index register

(d) Stack

Answer: (d)

89. An 8-bit microprocessor has the typical two way connected buffered lines which are called:

(a) Address bus

(b) Data bus

(c) Control bus

(d) Power lines

Answer: (b)

90. The advance microprocessor architecture’s term ‘Superscalar Architecture’ means:

(a) Scaling of application can be done with software

(b) The processor design enables the user to monitor the scaling performance of processor

(c) It includes more than one execution unit

(d) More perirerals can be added to the architecture

Answer: (c)