1. The instruction format for a processor has 1 bit for indirection, 6 bits for opcode and 9 bits for address of an operand. What is the maximum number of possible instructions, theoretically?
Answer: (c)
2. For a 32 bit processor with a 32 bit instruction format in which the first 10 bits contain the opcode and the remaining bits contain an operand address. What is the maximum directly addressable memory space?
(a) 16 MB
(b) 4 GB
(c) 1 KB
(d) 4 MB
(b) 4 GB
(c) 1 KB
(d) 4 MB
Answer: (a)
3. Consider the following statements:
1. Vertical micro-programmed control unit operates faster than horizontal micro-programmed control unit
2. Direct microprogramming results in very short micro-instructions
3. Hardwired control unit operates fastest
4. Micro-programming enables backward compatibility of programs
2. Direct microprogramming results in very short micro-instructions
3. Hardwired control unit operates fastest
4. Micro-programming enables backward compatibility of programs
Which of the above statements are correct?
(a) 3 and 4
(b) 1 and 2
(c) 2 and 3
(d) 1 and 4
(a) 3 and 4
(b) 1 and 2
(c) 2 and 3
(d) 1 and 4
Answer: (a)
4. If an instruction requires ′𝑖′ microseconds for execution and page fault requires ‘𝑗’ microseconds for resolving, and average page fault occurs every ‘𝑘’ instruction, then effective instruction time will be
(a) (𝑖+𝑗)∗𝑘
(b) (𝑖+𝑗)/𝑘
(c) 𝑖+(𝑗/𝑘)
(d) 𝑖+𝑗∗𝑘
(b) (𝑖+𝑗)/𝑘
(c) 𝑖+(𝑗/𝑘)
(d) 𝑖+𝑗∗𝑘
Answer: (c)
5. The cache memory of 1 𝑘 words uses direct mapping with a block size of 4 words. How many blocks can the cache accommodate?
(a) 128 words
(b) 256 words
(c) 512 words
(d) 1024 words
(b) 256 words
(c) 512 words
(d) 1024 words
Answer: (b)
6. How many NAND Gates are required to implement the Boolean function?
F = BC′+A(B +CD)
(a) 3
(b) 4
(c) 5
(d) 6
(b) 4
(c) 5
(d) 6
Answer: (c)
7. Which of the following is/are not the general attributes of horizontal micro-instructions?
1. Short formats
2. Ability to express a high degree of parallelism
3. Little encoding of the control information
1. Short formats
2. Ability to express a high degree of parallelism
3. Little encoding of the control information
(a) 1 only
(b) 2 only
(c) 3 only
(d) 1, 2 and 3
(b) 2 only
(c) 3 only
(d) 1, 2 and 3
Answer: (a)
8. If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in an 4×6 array, where each chip is 8𝑘×4 bits?
(a) 14
(b) 15
(c) 16
(d) 17
(b) 15
(c) 16
(d) 17
Answer: (d)
9. A 3 bit 𝑅/2𝑅, 𝐷 has a reference of 5 𝑉 . If the values of 𝑅 and the binary input are 15 𝑘Ω and 110 𝑉 respctively what is the output voltage?
(a) 0.375 𝑉
(b) 3.75 𝑉
(c) 4.25 𝑉
(d) 4.28 𝑉
(b) 3.75 𝑉
(c) 4.25 𝑉
(d) 4.28 𝑉
Answer: (b)
10. A 8086 microprocessor is interfaced to 8253 programmable interval timer. The maximum number by which the clock frequency on one of the timers is divided by
Answer: (b)
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